Regulators, or converters, including one or more switches, sometimes referred to as power switch(es), for transferring energy from an input, such as an AC or DC voltage or current source, to a regulated output are well known. In some regulators, sometimes referred to as switching regulators, the switch turns on and off to regulate the output. In other regulators, sometimes referred to as linear regulators, the switch operates in its active, or saturation region.
Common switching regulator configurations include Buck, Boost, Buck-Boost, flyback, SEPIC, Cúk, half bridge, and full bridge to name a few. As is also well known, various control methodologies for controlling conduction of the power switch(es) can be applied to switching regulators, including Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM), and for each of these control methodologies, various feedback and feed forward techniques are possible including voltage mode control and current mode control. Switching regulators are often used to provide a regulated current and/or voltage to drive a load.
Conventional Buck regulators generally contain a switch that conducts to transfer energy to an inductor during a first portion of each cycle and a diode (sometimes referred to as a freewheeling diode) that conducts during a second portion of each cycle to cause energy to be transferred from the inductor to the load. A variation of this conventional Buck regulator is referred to as a synchronous Buck regulator in which the freewheeling diode is replaced with a second switch. Although this configuration requires additional control circuitry to drive both of the switches, use of the second switch can result in improved efficiency.
An example synchronous Buck regulator 10 is shown in FIG. 1 to include switches 12, 14, here in the form of n-channel metal oxide semiconductor field effect transistors (MOSFETs or simply FETs), coupled between an input voltage source VIN 13 and a reference such as ground 15. A node SW 11 between the high side switch 12 and the low side switch 14 is coupled to an inductor 16 which stores energy for transfer to a load (not shown) coupled to an output terminal 18 at which a regulated output voltage VOUT is provided. An output capacitor 20 is also coupled to the output terminal 18.
Conduction of switching transistors 12, 14 is controlled by control circuit 48 and driver circuit 50. In the illustrated regulator 10, the control circuit 48 includes an error amplifier 26 that is responsive to the VOUT voltage 18 and to a reference signal 24 to generate a COMP signal 66 across a series-coupled resistor 28 and capacitor 30. The COMP signal 66 is coupled to an input of a comparator 32 that further receives a ramp signal from a summation element 36. More particularly, the summation element 36 sums a first ramp signal 64 with a feedback signal 40 that is proportional to the current through the switches 12, 14. An output of the comparator 32 provides a reset input to a flip-flop 34 that is set by a clock signal 58 from an oscillator 38. The output of the flip-flop 34 provides a feedback control signal HSON 52 that establishes on and off times of the high side switch 12 through the driver circuit 50, here in the form of a buffer 46, based on the output voltage VOUT 18. The HSON signal 52 is additionally coupled to a delay element 45 and a buffer 44 to establish on and off times for the low side switch 14, as shown.
In some embodiments, the control circuit 48 and driver circuit 50 can be provided in an integrated circuit (IC) package and the remainder of the regulator circuitry 51 can be external to the IC package. In this type of arrangement, the IC may be referred to generally as a driver IC.
It is desirable to operate switching regulators in a manner that enhances the electromagnetic compatibility (EMC) performance of the regulator. For example, in applications where a driver IC is used to drive one or more external transistors, it is generally desirable that the switching activity of the external transistor(s) cause as little electromagnetic interference (EMI) as possible to surrounding circuitry. It is known that fast slew rate (i.e., the rate of change of the switch drain to source, Vds, voltage per unit time) can contribute to EMI/EMC problems. However, it is also desirable that transitions between switching states be performed quickly with as little switching delay as possible since a slow slew rate and/or significant dead time (i.e., time when neither transistor is on, such as the time between the low side switch turning off and the high side switch turning on) can negatively impact regulator efficiency. It can be challenging to establish a switch slew rate and/or dead time that strikes an optimal balance between these competing requirements.
Slew rate is a function of various factors, such as the switch gate impedance, the switch capacitance, and the load current. In applications in which the switch capacitance and load current are well defined to within a relatively narrow range, the slew rate can be “tuned” by using external resistors, such as resistors 70, 72 in FIG. 1, in series with the respective gate connection to establish well controlled gate impedance. In general, in order to achieve substantially the same slew rate, smaller gate impedance is necessary for larger FETs (i.e., FETs with larger switch capacitance that drive larger loads) and larger gate impedance is necessary for smaller FETs (i.e., FETs with smaller switch capacitance that drive smaller loads). However, the difficulty of implementing such switch slew rate optimization can be compounded by use of a driver IC to drive a variety of external switches for a variety of loads, since the switch capacitance and load current can vary.
It is also desirable to operate switching regulators in a manner that optimizes the dead time. If the dead time is too long, the body diode of the low side switch 14 will conduct, which decreases the regulator efficiency due to switching and conduction losses of the diode and the reverse recovery time associated with turning off the diode. On the other hand, a dead time that is too short can result in both the high side switch 12 and the low side switch 14 being on at the same time, which can cause undesirable shoot through currents that can adversely impact EMI performance and efficiency.
Dead time is affected by various parameters of the driven switches 12, 14, such as the threshold voltages, gate capacitance, and gate resistance. Thus, optimization of the dead time is challenging when such parameters are not well known or tightly controlled, such as when using a driver IC to drive a range of external FET switches 12, 14. Furthermore, this optimization can be even more challenging since these FET parameters are influenced by other factors, such as load current, input voltage, output voltage, and temperature variations.